The present invention relates to integrated circuits. More particularly, the present invention relates to a capacitor formed in a vertical manner.
Deep trench capacitors are known to require the deposition and planarization of doped polysilicon using techniques such as chemical mechanical planarization (“CMP”) to achieve a flat surface over a silicon layer after its deposition. However, utilizing CMP is not ideal because it involves multi-stage processes and is relatively expensive. Other capacitors are also known to have many mask levels and a complex process flow.